Method for ashing

ABSTRACT

The present invention provides an ashing method using rapid heat transfer under high pressure. The present method, applicable to all photoresist ashing processes, can rapidly remove hardened photoresists without popping at the ashing step by baking high dose ion implanted silicon substrate on a hot plate, enhancing the ashing quantity, by drastically reducing the ashing process time, while allowing conventional equipments to be used further. The present method comprises an in situ baking step, wherein a silicon substrate is baked for a predetermined time period under a pressure of 10 Torr or more while it is placed on a hot plate; a vacuumizing step, wherein a stable vacuum status is achieved while the silicon substrate is placed on the hot plate; a gas processing step, wherein selected reaction gas is introduced into a reaction chamber; and an ashing step, wherein plasma is generated until almost all of the photoresists are removed.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method for ashing, and in particular,to a semiconductor wafer ashing method, wherein a semiconductorsubstrate is baked in a high temperature on a hot plate and the hardenedphotoresists are rapidly removed without popping at the step of ashing,allowing an enhancement of the ashing quantity through a drasticreduction of the time required for a wafer ashing process, whileallowing further use of a conventional ashing equipment.

BACKGROUND OF THE INVENTION

A photo lithography process, which is one of manufacture processes ofsemiconductor devices, comprises the steps of spin coating ofphotoresists for the purpose of forming a photoresist layer on asemiconductor substrate; of selective exposuring of the photoresistlayer; of developing the exposed photoresist layer to form a photoresistpattern; of etching or introducing impurities to areas of thesemiconductor substrate not covered by the photoresist and of ashingprocess in which the photoresist pattern used as a mask in the dopantimplantation step is removed.

An ashing process using plasma comprising an oxygen base or an oxygenion is a process for removal of photoresist pattern. A conventionalashing process is carried out by introducing plasma in a reactionchamber, in which a wafer has been heated under low pressure via anappropriate heating means. Since an ashing rate in an ashing process isproportional to the temperature, ashing processes were carried out inhigh temperatures. Actually, between 80° C. and 300° C., thephotoresists are changed drastically to activated energy state inproportion to the increase of temperature, while the activated energydecreases at temperatures over 300° C.

In particular, the material on the upper layer of the photoresistpattern undergoes a chemical change at the step of ion implantation, tobecome hardened. An ashing process after the ion implantation is carriedout in a high temperature as described above, and the phenomenon ofpopping occurs at a temperature of ca. 120° C. or over, wherein thehardened photoresist layer is destroyed due to the expansion of theevaporated material at the lower part of the hardened photoresist. Suchphenomenon is highly undesirable, for popping causes contamination ofthe wafer surface as well as the inner surface of the ashing equipmentand rejection of the wafer, resulting in raising of the production costsand a lowering of productivity by extending the process time. On theother hand, performing an ashing process at a low temperature to avoidsuch popping would result in a lower ashing efficiency, because such aprocess requires a longer processing time.

A conventional ashing equipment removes hard photoresists in a lowtemperature using a lamp heating device as illustrated in FIG. 1, andthen, removes the remaining soft photoresists by bringing thesemiconductor substrate to a high temperature.

FIG. 2 illustrates a method of removing photoresists after theconventional ion implantation, in the initial step of which process(210) O₂ gas, N₂ gas, and CF₄ gas are filled in a reactor and a vacuumdegree of about 1 Torr to 10 Torr is maintained. In the first ashingstep (220), a semiconductor substrate is heated to reach a temperatureof 100° C. to 150° C. using a lamp or a hot plate and then, the hardphotoresists are removed. In the second ashing step (230), the remainingsoft resists are removed. The numeral 240 in FIG. 2 indicatestemperature change of the wafer. Further, the numeral 250, being a graphindicating the generated gas caused by the above reaction, showsquantity of the removed photoresists via quantity of the gas generatedby the above photoresists removing reaction.

An ashing process for a dose ion implanted silicon substrate is alsopossible with a conventional ashing equipment. However, problems withsuch a procedure are that as diameter of the silicon substrate gettinggreater, the equipment cost increases and that a more complicatedelectric as well as mechanical structures are necessary for maintenanceof such an equipment. Accordingly, the unit price relative to theproductivity rises.

DETAILED DESCRIPTION OF THE INVENTION

The present invention, conceived to solve the aforementioned problems,aims to provide a semiconductor wafer ashing method capable of removingeffectively and rapidly hardened hard photoresists without popping.

Another objective of the present invention is to provide a semiconductorwafer ashing method which can enhance the efficiency of the ashingprocess.

In order to achieve the above objectives, the prpesent inventionprovides an ashing method comprising a first step, wherein a siliconsubstrate is in situ baked while it is put on a high-temperature hotplate, and a subsequent ashing step, wherein soft photoresists as wellas hard photoresists are ashed simultaneously, using plasma. The presentinvention, being applicable to any photoresist ashing process, showsespecially high efficiency with dose ion implanted silicon substrates.

The ashing method in accordance with the present invention comprises, incontrast to the conventional ashing method, an additional step of insitu baking (300-1) of a silicon substrate under high pressure prior tothe step of ashing, as shown in FIG. 3. The process proceeds further,under conditions similar to those of the conventional method, to avacuum processing step (300-2) and to a gas processing step (300-3). Inthe step of ashing (310), following the in situ baking step (300-1), thevacuum processing step (300-2) and the gas processing step (300-3), thehard photoresists are removed at once together with the softphotoresists in a process using the power of plasma. Moreover, anover-ashing step (320) may be added to ensure complete removal of theentire photoresists.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the construction of a prior art silicon substrate ashingequipment.

FIG. 2 shows a process sequence chart based on the temperature of aconventional dose ion implanted silicon substrate.

FIG. 3 shows a process sequence chart based on the temperature of a doseion implanted silicon substrate in accordance with the presentinvention.

FIGS. 4 through 8 are schematic diagrams showing removal of photoresistsin the course of the ashing process on a dose ion implanted siliconsubstrate in accordance with the present invention.

FIG. 9 shows SEM photos of a via-etching substrate after an ashingprocess in accordance with the conventional method.

FIG. 10 shows SEM photos of a via-etching substrate after an ashingprocess in accordance with the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A description of the preferred embodiments of the present invention isgiven below making reference to the accompanying drawings, for a moreclear understanding of the present invention.

A semiconductor wafer ashing method as per the present inventionproceeds in sequences as illustrated in FIG. 3.

In the in situ baking step (300-1), the photoresists are removed basedon the fact that, when a silicon substrate is put on a high-temperaturehot plate in a high pressure reaction chamber, the soft photoresists areso rapidly contracted that no thermal expansion occurs. To elaborate,the substrate is put on a hot plate with a temperature from 200° C. to300° C. under a pressure of 10 Torr or more, and maintained for apredetermined period of time. The maintenance time at this step of insitu baking, though it may be set appropriately depending on thesubstrate conditions such as quantity of the doping, is preferably fiveto twenty seconds, in which case temperature of the substrate risessteeply as shown in FIG. 3.

Especially, once five seconds have elapsed after a dose ion implantedwafer was put on a high-temperature hot plate, the soft photoresistscontract, color of the photoresists changes, and no popping occurs.Since the soft photoresists contain volatile materials, such volatilematerials shall completely be extinguished through a baking of twentyseconds or less prior to a plasma generation.

At the step of vacuum processing (300-2), the reaction chamber isbrought to a stable vacuum status while the silicon substrate is put ona high-temperature hot plate. The temperature change of the siliconplate during this procedure is as shown in FIG. 3. This step isperformed in conditions similar to the conventional methods.

At the step of gas processing (300-3), processing gas is introduced intothe reaction chamber while the silicon substrate is put on ahigh-temperature hot plate to reach a level of pressure appropriate tothe processing conditions, and then the pressure is maintained. Thetemperature change of the silicon plate during this procedure is asshown in FIG. 3. The processing gas used here may be the same as thatused in a conventional ashing method.

No plasma is used in any of the above steps: the high-pressureprocessing step (300-1), the vacuum processing step (300-2), and the gasprocessing step (300-3).

At the ashing step (310) the process proceeds by generating plasma whilethe temperature of the silicon substrate put on a high-temperature hotplate maintains a high level. Here, the processing conditions are thesame as those in the second ashing step of a conventional ashing method,with the difference that the hard photoresists 410 are removed togetherwith the soft photoresists 420 at this step in the method of the presentinvention.

The step of over-ashing (320), which is for providing a margin, has thesame processing conditions as the ashing step (310).

Further, from the gas generation graph (330) illustrating the gasgenerated during the photoresists removal reaction, it can be seen thatthe quantity of gas generated by the chemical reaction maintains over acertain level at the step of ashing (310), while it is reduced at thestep of over-ashing (320), where almost all of the photoresists havealready been removed.

Temperature of the silicon substrate (340) rises rapidly at the step ofin situ baking (300) and maintains a high level at the step of ashing(310) as shown in FIG. 3.

FIGS. 4 through 8 are diagrams showing removal of photoresists 400 inthe course of the ashing process on a dose ion implanted siliconsubstrate 430 in accordance with the present invention. FIG. 4 shows aphotoresist 400 as coated on a silicon substrate at a step prior to thein situ baking step (300). FIG. 5 shows an ion implantation procedure ofa dopant 440 containing P, B, or As on a silicon substrate 430 at a stepprior to the in situ baking step (300). FIG. 6 shows the step of in situbaking (300) after implantation of a dopant, wherein hard photoresists410 as well as soft photoresists 420 coexist on the silicon substrate430. FIG. 7 shows a state, in which the hard photoresists 410 areremoved at the ashing step (310), while FIG. 8 shows a state, in whichthe soft photoresists 420 are removed.

Next, it was confirmed as to whether any popping had occurred on thedose ion implanted silicon substrate while the ashing method as per thepresent invention was carried out. The experiment conditions for suchconfirmation and the results are shown in Table 1 below. TABLE 1 In situIn situ baking baking Ashing Plasma Hot plate HDI time pressure pressurepower O₂ H₂N₂ Temperature Wafer (second) (Torr) (Torr) (W) (sccm) (sccm)(C.) Result 31P + 6.0E15 10 760 1.5 1500 2000 200 230/250/270 No popping31P + 6.0E15 10 760 1.5 1500 2000 400 230/250/270 No popping 31P +8.0E15 10 760 1.5 1500 2000 500 230/250/270 No popping 31P + 8.0E15 10760 1.5 1500 2000 500 230/250/270 No popping 31P + 1.0E16 10 760 1.51500 2000 500 230/250/270 No popping 31P + 1.0E16 10 760 1.5 1500 2000500 230/250/270 No popping 75As + 3.5E15 10 760 1.5 1500 2000 500230/250/270 No popping 31P + 1.0E14 10 760 1.5 1500 2000 500 230/250/270No popping 75As + 8.0E15 10 760 1.5 1500 2000 500 230/250/270 No popping31P + 1.0E14 10 760 1.5 1500 2000 500 230/250/270 No popping

Conditions such as pressure, microwave, O₂ gas, H₂N₂ gas, temperature asshown in Table 1 have been used for testing whether or not a popping hasoccurred. When a dopant containing P or As was used under a pressure of1500 mTorr, in a plasma power of 1500 W, with 2000 sccm of oxygen gasand with an amount of H₂N₂ gas ranging from 200 sccm to 500 sccm, nopopping has occurred.

After that, the ashing method as per the present invention was comparedwith the conventional ashing method in respect to the ashing ofvia-etching substrates. The process conditions for the conventionalmethod are as shown in Table 2, while the corresponding conditions forthe method of the present invention are as shown in Table 3. TABLE 2Ashing Plasma Hot plate Processing pressure power O₂ N₂ temperature Time(Torr) (W) (sccm) (sccm) (C.) (second) 1 2500 7000 800 250 230

TABLE 3 In situ baking In situ Ashing Plasma Hot plate Processingpressure baking time pressure power O₂ N₂ temperature time (Torr)(second) (Torr) (W) (sccm) (sccm) (C.) (second) 760 10 1 2500 7000 800250 60

From the above two Tables, it can be seen that the processing time asper the method of the present invention amounts to 60 seconds, while thecorresponding processing time under the same ashing conditions requiredby the conventional method is 230 seconds.

The scanning electron microscopy (SEM) photos taken after the aboveprocesses are shown in FIGS. 9 and 10. While FIG. 9 shows SEM photosafter an ashing process in accordance with the conventional method, FIG.10 shows SEM photos after the in situ baking method as per the presentinvention has been used. In the above two photos, no significantdifference can be detected between the SEM photos as per theconventional method and the SEM photos as per the present method.

Accordingly, the method of the present invention is advantageous in thata popping due to the discrepancy in thermal expansion coefficients ofthe hard photoresist layer and of the soft photoresist layer at the insitu baking step is prevented, and in that the hard photoresists areremoved together with the soft photoresists at the ashing step.

INDUSTRIAL APPLICABILITY

As described above, the present invention provides an ashing methodcapable of removing all photoresists, in particular, hardenedphotoresists, rapidly at the step of ashing without any popping, throughan in situ baking of the does ion implanted silicon substrate on ahigh-temperature hot plate, resulting in an enhancing of the processquantity of the ashing and a reduction in the maintenance costs of theashing equipment by drastically shortening the processing time.

1. An ashing method comprising: an in situ baking step, wherein asilicon substrate is baked for a predetermined period of time under apressure of 10 Torr or more while said silicon substrate is placed on ahot plate; a vacuumizing step, wherein a stable vacuum status isachieved while said silicon substrate is placed on said hot plate; a gasprocessing step, wherein selected reaction gas is introduced into areaction chamber; and an ashing step, wherein plasma is generated untilalmost all of the photoresists are removed.
 2. The ashing method as setforth in claim 1, wherein the temperature of said hot plate is from 200°C. through 300° C.
 3. The ashing method as set forth in claim 2, whereinthe temperature of said hot plate is from 230° C. through 270° C.
 4. Theashing method as set forth in claim 1, wherein said predetermined periodof time at said in situ baking step is longer than five seconds, but notlonger than twenty seconds.
 5. The ashing method as set forth in claim1, wherein said reaction gas comprises one or more of O₂, N₂, H₂N₂, O₃,or CF₄.
 6. The ashing method as set forth in claim 1, wherein saidsilicon substrate is dose ion implanted.
 7. The ashing method as setforth in claim 1, wherein said silicon substrate is a via-etchedsubstrate.
 8. The ashing method as set forth in claim 1, wherein saidsilicon substrate is a pad-etched substrate.
 9. The ashing method as setforth in claim 1, comprising additionally an over-ashing step, in whichplasma is continuously generated even after almost all of thephotoresists have been removed by plasma generated at said ashing step.